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Noise Cancellation Logic by PotatoSemi
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Advantage:
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Very high output frequency. (The max. frequency can reach process max. frequency.)
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Switching noise can be eliminating by note to note noise cancellation.
(Noise from note A & noise from note A bar will cancel each other. Noise from note B & noise from note B bar will cancel each other. Noise from note C & noise from note C bar will cancel each other. Noise from note out & noise from note out bar will cancel each other.)
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Rail to rail output signals.
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Without switching noise, logic output signal can be much stronger then other logic output signal.
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Low jitter.
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Output signals can drive long distance.
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No error bit.
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No static current.
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Design is very similar to normal CMOS logic. It can be used for high frequency & high performance VLSI design.
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Disadvantage:
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More complicate design then normal CMOS logic
Bigger die size then normal low speed CMOS logic.
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Example:
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Potato Semiconductor ICs are using this technology such as GHz 74 series logic, clock buffer, bus switch, signal translator.
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How Does PotatoSemi Kill inside Noise of IC |
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How does the new technology work
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By using our special IO interface, logic cells & design rule, we can convert most of existing Logic chips into much higher frequency than it was before. After we convert the standard chips, all chips become much more reliable, much less noise and much higher running frequency. |
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Next generation logic cell IP |
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How to improve IC performance |
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 1. Improve package |
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DIP - SMC - BGA - Flip Chip
Improve package for reduce inductance |
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2. Improve process |
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0.5um, 0.35um, 0.18um, 0.13um, 0.09um, 0.065um,
CMOS, BICMOS, SOI
Improve process for reduce transistor's resistance & capacitance.
This will reduce RC charge & discharge time.
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3. Improve architecture |
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x86, dual core, 64 architecture etc. |
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4. Improve circuit structure |
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Using new circuit structure from PotatoSemi
What’s new for CMOS Logic
New CMOS inverter, new NAND gate, new NOR gate, New flip flop,
New logic cells are designed to handle RLC charge & discharge.
New logic gate will eliminate switching noise to improve IC performance
Regular CMOS logic cells such as inverter, NAND gate, NOR gate, XOR gate are designed 50 years ago. They are perfect to provide logic function by RC charge & discharge. However, they are not suitable for RLC charge & discharge. If inductance is involved, high switching noise will be generated by the normal logic cells. People spend hundred thousands dollars to reduce inductance from IC package, but inductance is still there. In the real world, inductance is from the nature. They are always there.
Potato Semiconductor's products are using the next generation logic cells.
Those new cells are designed to handle RLC charge & discharge. Switching noise will be eliminated by each cell itself. Our design is extremely simple, but effective.
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| Potato CMOS logic V.S. Normal high noise CMOS logic |
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| Next generation GHz CMOS Output IP |
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How to improve IC performance |
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GHz CMOS Output IP
 CMOS technology has been widely used for more than 50 years. It delivers low cost with high yield; however due to the unbalanced CMOS structure, it will generate high noise into power and ground. In the past 50 years of IC history our GHz CMOS output driver is the only technology that will reduce your chip internal ground and power noise without sacrificing your output performance. Our low noise technology allows the output frequency to be 7 to 10 times faster than anyone else in the world. In addition, this low noise technology allows any ICs with our output drivers to deliver accuracy without errors. The example below shows the output signal from our standard logic 74G32. The VCC is 3V. The output frequency from the measurement is 2 GHz with probe load. The maximum frequency will be more than 2 GHz. VPP is 2.075V, Vhigh is 2.175V and Vlow is 100 mV.
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Please contact us if you'd like to improve your IC products. |
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RoHS compliant
