Potato Semiconductor Corporation

74G clock buffer

Feedback from PotatoSemi:
I will like to share & discuss some technical information with you. When you use our clock buffer, we prefer that you can connect the entire clock buffer outputs without any open circuit. For example, when you use 3807 1 to 10 clock buffer, the best case will be 10 outputs connect to 10 similar loads. If in case that you only use 9 outputs, please add a dummy loading capacitor to the 1 left open output to make the termination. So the 10 output signals will switch about the same time. Any output signal without loading will switch much faster then the other output signal with loading. Much faster switching & delay time from open output signal will increase noise & jitter. The equal loading & same output trace length are important when you use clock buffers. Please let me know if you have any question or comment.

Comments:
I understand your comment and usually terminate unused outputs. However, I have wondered what the tradeoff is between equalizing loading and delta I noise.
If you leave the unused outputs open circuited, you will get a noise spike that is not coincident with the other channels. However, the current spike is mostly due to the overlap of PMOS/NMOS switching. If you add a load capacitance, you then add the current spikes from charge/discharging the load capacitance to the current spikes. How large are the two components?
Do you have any waveforms that compare the two situations?

Feedback from PotatoSemi:
CMOS circuits have been used for over 50 years. All the CMOS circuit ICs have spike except potato chips. We have the technology to kill the spike so our products can run much higher frequency. You can see the comparison from the attached file. The left side is our 3807 with noise kill circuit. The right hand side is the normal 3807. All of them are running in same condition with 10 outputs switching at the same time. The output is driving 15pf loading. Now, you can see why the 3807 from other semiconductor companies can not run beyond 200MHz. Spike is the only reason. People also call them ground bounce or noise. Jitter is also related to the noise. They are all the same thing. We make our noise kill circuit perfect matching 8pf loading. If your loading is more far away, the chip ground noise will slightly higher. You can see the attached file for example. That output is driving 15pf loading. This is the reason we recommend our customers to add 8pf termination capacitor to the open output. This termination capacitor is only good for our GHz CMOS output circuit. Termination capacitor is no use to the regular CMOS outputs. This is just like what you said. They are going to be noisy anyway which does not matter you add the capacitor or not.

Comments:
Thanks for the information. In my specific application, I am driving a 50 ohm transmission line with an AC coupled 50 ohm termination. Do you still recommend using the same load as a dummy termination for unused outputs?

Feedback from PotatoSemi:
Yes. I still recommend adding 8pf dummy termination for unused outputs. Our noise kill circuit will work anyway which does not matter the loading is 0pf or 15pf. The 8pf dummy is only for the fine tune. Of cause, the best scenario is no dummy output. All the dummy outputs will waste power..

PotatoSemi GHz TTL Logic- Clock Buffer

Regular Clock Buffer

Advantage
1. Easy to use.
2. Clock source is from crystal oscillator.
3. Only need decupling capacitor. No extra component is needed.
4. No static current.

Disadvantage
1. High Noise.
2. Low operating frequency.
3. Large Propagation Delay.
3. High jitter.
4. Week output signal.
5. Signal is not able to run through cable.

Zero Delay Clock Buffer

Advantage
1. Zero Delay.

Disadvantage
1. Shift clock source from crystal oscillator to PLL local oscillator.
2. High Noise.
3. Low operating frequency.
4. High jitter.
5. Week output signal.
6. Signal is not able to run through cable.

ECL Clock buffer

Advantage
1. Small propagation delay.
2. Clock source is from crystal oscillator.
3. Run high frequency.
4. Low noise.
5. Low jitter.
6. Can run through cable.

Disadvantage
1. Difficult to use.
2. Need many extra components such as 50 ohm loading resistors.
3. Need two wires to represent one bit.
5. Waste PCB space.
5. Current source design. High static current.
6. Burn electricity power when the system is idle. Waste energy.

The Next Generation GHz CMOS Clock Buffer
(PotatoSemi Clock Buffer)

Advantage
1. Small propagation delay.
2. Clock source is from crystal oscillator.
3. Strong output signal.
4. Run high frequency.
5. Low noise.
6. Low jitter.
7. Can run through cable.
8. Only one wire for one bit.
9. Easy to use.
10. Embedded decupling capacitor.
11. Power up and run. No extra component is needed.
12. Voltage source design. No static current.
13. Do not waste power. Power saving. Environment friendly.

PO100HSTL23A

We just finished testing this device (PO100HSTL23A) in several circuits
on a new product and found its performance to be OUTSTANDING. We are
definitely going to look at using it in our other products to improve
yield and jitter performance. The ability to drive different impedance
loads with well behaved "fast" edges (on-board as well as coax cables)
with very little power supply noise is amazing.

I just want to thank your company for making this product. We will
seriously be looking at your other products to see how we can use them
in existing and future products.

Lastly, if you want to send us some literature on how you pulled this
off I would be very interested. I would also appreciate any Spice
models if you have any available. They can be pseudo models as long as
their transmission line properties are retained.

Thanks,

--
Chase Scientific Company